Senior FPGA Engineer CONTRACT 40 hours weekly 12+ months Work Schedule: Onsite 7:30AM to 5:00PM Monday-Thursday. 7:30AM to 4:00PM Every other Friday. Off the other Friday.

(3) OPEN POSITIONS Over time is authorized at 1.5X Rate The Senior FPGA Engineer will design new FPGAs or update existing FPGAs, as business conditions dictate. The FPGA design process includes requirements definition, conceptual design, detailed design, and design verification.

The Senior FPGA Engineer should be detail-oriented, self-driven, and able to work independently or with a team. This position requires expert knowledge of the following items: VHDL ModelSim/Questa Sim Clock Domain Crossing (CDC) Analysis Static Timing Analysis (STA) Self-checking testbenches The position could also involve: System Verilog.